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Manual for VHDL Lab for 6th Semester.


BASIC GATE implementations Edit

The following gives the implementations of Basic gates in VHDL

OR Gate Edit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity orgate is

    Port ( x,y : in std_logic;

           z : out std_logic);

end orgate;

architecture Behavioral of orgate is

begin
	 z<=x or y;

end Behavioral;


AND Gate Edit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity andgate is
    Port ( x,y : in std_logic;

           z : out std_logic);

end andgate;

architecture Behavioral of andgate is

begin
	 z<=x and y;

end Behavioral;


NOR Gate Edit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity norgate is
    Port ( x,y : in std_logic;

           z : out std_logic);

end norgate;

architecture Behavioral of norgate is

begin
	 z<=x nor y;

end Behavioral;


NAND Gate Edit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity nandgate is
    Port ( x,y : in std_logic;

           z : out std_logic);

end nandgate;

architecture Behavioral of nandgate is

begin
	 z<=x nand y;

end Behavioral;


XOR Gate Edit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xorgate is
    Port ( x,y : in std_logic;

           z : out std_logic);

end xorgate;

architecture Behavioral of xorgate is

begin
	 z<=x  xor y;

end Behavioral;


NOR Gate Edit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xnorgate is

    Port ( x,y : in std_logic;

           z : out std_logic);

end xnorgate;

architecture Behavioral of xnorgate is

begin
	 z<=x xnor y;

end Behavioral;


NOT Gate Edit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity notgate is
    Port ( x : in std_logic;

           z : out std_logic);

end notgate;

architecture Behavioral of notgate is

begin
	 z<=not y;

end Behavioral;

VHDL programs for the following combinational circuits Edit

2 to 4 Decoder. Edit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity dec1 is
    Port ( x : in bit;
           y : in bit;
           e : in bit;
           z : out bit_vector(3 downto 0));
end dec1;

architecture Behavioral of dec1 is
signal xc,yc:bit;
begin
xc<=not x;

yc<=not y;

z(0)<=e and xc and yc;

z(1)<=e and xc and y;

z(2)<=e and x and yc;

z(3)<=e and x and y;

end Behavioral;



===library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity encod is
    Port ( din : in std_logic_vector(7 downto 0);
           dout : out std_logic_vector(2 downto 0));
end encod;
 architecture Behavioral of encod is
 begin
 process(  din)
variable temp:std_logic_vector(2 downto 0);
begin
     case din is
when "00000001" => temp:= "000"; 

when "00000010" => temp:= "001";

when "00000100" => temp:= "010";

when "00001000" => temp:= "011";

when "00010000" => temp:= "100";

when "00100000" => temp:= "101";

when "01000000" => temp:= "110";

when "10000000" => temp:= "111";

when others => null;
    end case;
 dout<= temp;
end process;
  end Behavioral;

8 to 3 Priority Encoder Edit

8 to 1 Multiplexer Edit

4-bit Binary to Gray code converter Edit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity mux2 is
   
  Port ( d : in std_logic_vector(7 downto 0);
      
  en : in std_logic;
        
  abc : in std_logic_vector(0 to 2);         

  y : out std_logic);

end mux2;


architecture Behavioral of mux2 is

 begin

 process (en,d)

 variable t1: std_logic;

 begin

 if (en='0') then

      case abc is

            when "000"=> t1:=d(0);

            when "001"=> t1:=d(1);

            when "010"=> t1:=d(2);

            when "011"=> t1:=d(3);

            when "100"=> t1:=d(4);

            when "101"=> t1:=d(5);

            when "110"=> t1:=d(6);

            when "111"=> t1:=d(7);

            when others =>t1:='0';

      end case; 

 else

      t1:='0';

 end if;

 y<=t1;

 end process;

 end Behavioral;

De-multiplexer Edit

Comparator Edit

VHDL program to realize Full Adder in the following modeling styles Edit

Structural Modeling Edit

Data Flow Model Edit

Behavioral Model Edit

--The IEEE standard 1164 package, declares std_logic, etc. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;


Entity Declarations -------------------------

entity FA is port( A,B,Cin : in STD_LOGIC; SUM,CARRY : out STD_LOGIC ); end FA;


Architecture Declarations ----------------------

architecture BEHAVIOR of FA is begin process(A,B,Cin) begin SUM<= A XOR B XOR Cin; CARRY<= (A AND B) OR (Cin AND A)OR (Cin AND B); end process; end BEHAVIOR;

VHDL code for 8-bit ALU Edit

VHDL code for SR, JK, D and T- Flip-flops Edit

VHDL code for 4- bit binary and BCD, Synchronous and Asynchronous counters Edit

Interfacing experiments: Edit

Stepper Motor Edit

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;


use IEEE.STD_LOGIC_ARITH.ALL;


use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity STEPPERnew is


Port ( dout : out std_logic_vector(3 downto 0);


clk,reset: in std_logic;

row:in std_logic_vector(1 downto 0);

dir:in std_logic);


end STEPPERnew;


architecture Behavioral of STEPPERnew is

signal clk_div : std_logic_vector(25 downto 0);


signal clk_int: std_logic;

signal shift_reg : std_logic_vector(3 downto 0);


begin


process(clk)


begin


if rising_edge (clk) then


clk_div <= clk_div + '1';


end if;


end process;

clk_int<=clk_div(21) when row="00"else

clk_div(19) when row="01"else

clk_div(17) when row="10"else

clk_div(15) ;


process(reset,clk_int,dir)

begin


if reset='0' then


shift_reg <= "1001";

elsif rising_edge(clk_int) then


if dir='0' then

shift_reg <= shift_reg(0) & shift_reg(3 downto 1);

else

shift_reg<=shift_reg(2 downto 0) & shift_reg(3);

end if;

end if;

end process;

dout <= shift_reg;

end Behavioral;

--DC Motor Edit

Library IEEE; use IEEE.std_logic_1164.all;


use IEEE.STD_LOGIC_UNSIGNED.all; Library UNISIM;

use UNISIM.vcomponents.all;

entity dcmotor is generic(bits : integer := 8 ); -- number of bits used for duty cycle. -- Also determines pwm period. port ( CLK: in STD_LOGIC ; -- 4 MHz clock

RESET,DIR: in STD_LOGIC; -- dircntr

pwm : out std_logic_VECTOR(1 DOWNTO 0);

rly: out std_logic;

ROW: in STD_LOGIC_VECTOR(0 to 3) ); -- this are the row lines

end dcmotor;

architecture dcmotor1 of dcmotor is

signal counter : std_logic_vector(bits - 1 downto 0):="11111110";

signal DIV_REG: STD_LOGIC_VECTOR (16 downto 0); -- clock divide register

signal DCLK,DDCLK,datain,tick: STD_LOGIC; -- this has the divided clock.

signal duty_cycle: integer range 0 to 255;

signal ROW1 : STD_LOGIC_VECTOR(0 to 3); -- this are the row lines

begin

-- select the appropriate lines for setting frequency

CLK_DIV: process (CLK, DIV_REG) -- clock divider

begin

if (CLK'event and CLK='1') then

DIV_REG <= DIV_REG + 1;

end if;

end process;

DDCLK<=DIV_REG(12);



END OF CLOCK DIVIDER ---------------------------------------------

tick <= row(0) and row(1) and row(2) and row(3);

process(tick)

begin

if falling_edge(tick) then

case row is

when "1110" => duty_cycle <= 255 ; --motor speed 1

when "1101" => duty_cycle <= 200 ; --motor speed 2

when "1011" => duty_cycle <= 150 ; --motor speed 3

when "0111" => duty_cycle <= 100 ; --motor speed 4

when others => duty_cycle <= 100;

end case;

end if;

end process;

process(DDCLK, reset)

begin

if reset = '0' then

counter <= (others => '0');

PWM<="01";

elsif (DDCLK'event and DDCLK = '1') then

counter <= counter + 1;

if (counter >= duty_cycle) then

pwm(1) <= '0';

else

pwm(1) <= '1';

end if; end if;

end process;

rly<=DIR --motor direction control

end dcmotor;
Library IEEE; 

use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

Library UNISIM;

use UNISIM.vcomponents.all;

entity dcmotor is
generic(bits : integer := 8 ); -- number of bits used for duty cycle.
                               -- Also determines pwm period.
port ( CLK: in STD_LOGIC );      -- 4 MHz clock

RESET,DIR: in STD_LOGIC; -- dircntr

pwm : out std_logic_VECTOR(1 DOWNTO 0);

rly: out std_logic;

ROW: in STD_LOGIC_VECTOR(0 to 3) ); -- this are the row lines

end dcmotor;

architecture dcmotor1 of dcmotor is

signal counter : std_logic_vector(bits - 1 downto 0):="11111110";

signal DIV_REG: STD_LOGIC_VECTOR (16 downto 0); -- clock divide register

signal DCLK,DDCLK,datain,tick: STD_LOGIC; -- this has the divided clock.

signal duty_cycle: integer range 0 to 255;

signal ROW1 : STD_LOGIC_VECTOR(0 to 3); -- this are the row lines

begin

-- select the appropriate lines for setting frequency

CLK_DIV: process (CLK, DIV_REG) -- clock divider

begin

if (CLK'event and CLK='1') then

DIV_REG <= DIV_REG + 1;

end if;

end process;

DDCLK<=DIV_REG(12);


---------------------------- END OF CLOCK DIVIDER ---------------------------------------------

tick <= row(0) and row(1) and row(2) and row(3);

process(tick)

begin

if falling_edge(tick) then

case row is

when "1110" => duty_cycle <= 255 ; --motor speed 1

when "1101" => duty_cycle <= 200 ; --motor speed 2

when "1011" => duty_cycle <= 150 ; --motor speed 3

when "0111" => duty_cycle <= 100 ; --motor speed 4

when others => duty_cycle <= 100;

end case;

end if;

end process;

process(DDCLK, reset)

begin

if reset = '0' then

counter <= (others => '0');

PWM<="01";

elsif (DDCLK'event and DDCLK = '1') then

counter <= counter + 1;

if counter >= duty_cycle then

pwm(1) <= '0';

else

pwm(1) <= '1';

end if; end if;

end process;

rly<=DIR --motor direction control

end dcmotor1;

Relay Control Edit

Counter on LCD Display Edit

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